1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit that can control a signal delay amount.
2. Related Art
The data transfer rate during data input/output operations of a semiconductor integrated circuit is generally sensitive to variations in environmental and process conditions. This can cause significant design concerns, as well as a number of problems in terms of device performance.
This is due to conflicting parameters in the data transfer rate. Examples of the conflicting parameters include an access time (tAC) and a data retention time (tOH), which are defined in the DRAM or SRAM specification.
The access time (tAC) refers to the amount of time required from the input of a clock to data output, and the data retention time (tOH) refers to the amount of time that data must be retained after the input of a clock.
In order to meet the requirement of the access time (tAC), the data transfer rate must be as high as possible. On the other hand, in order to meet the requirement of the data retention time (tOH), the data transfer rate must be maintained at a low level. Thus, since the two parameters have conflicting characteristics, it is difficult to ensure an appropriate margin.
In addition, when certain process conditions change or certain unintended characteristic variations occur during the process due to process variables, the access time (tAC) and the data retention time (tOH) may be changed out of the specification, resulting in a failure.
Problems with the conventional art can be shown through the timing diagram of FIG. 1. When complying with the process conditions of a characteristic A (General Characteristic), the access time (tAC) is shorter than the access time provided in the specification (tAC spec), and the data retention time (tOH) is longer than the data retention time provided in the specification (tOH spec). Thus, the requirements of the access time (tAC) and the data retention time (tOH) are met.
However, where the operation characteristics of MOS transistors are varied because several process conditions are varied or unintended characteristic variations occur due to process variables, and if the data input/output time has a characteristic B (High-Speed Characteristic), the data retention time (tOH) falls short of the amount of time provided in the specification, resulting in a failure. Furthermore, when the data input/output time has a characteristic C (Low-Speed Characteristic), the access time (tAC) lapses beyond the amount of time provided in the specification, resulting in a failure.
A conventional method for solving these problems associated with variations of environmental conditions and process conditions is described below with reference to FIG. 2. A basic delay amount is set based on basic process condition values, so that the delay amount of data input/output signals may be adjusted. Capacitors MN1, MN2, MP1 and MP2 matched to those values are connected to a circuit. Capacitors MN1 and MP1 are set to a turned-on state, and capacitors MN2 and MP2 are set to a turned-off state. In the event of a change in process conditions or a change in the data transfer rate during the data input/output operation caused by variance in the operation characteristics of the MOS transistors from unintended variations of the process variables, the total delay amount is readjusted by additionally connecting capacitors MN1, MN2, MP1 and MP2 to the circuit by using metal revision by a focus ion beam (FIB).
However, it is difficult to respond accurately to changes in process conditions or changes caused by process variables by using metal revision by FIB, since it may be used only a limited number of times. Furthermore, the metal revision process requires a lot of time and thus compromises the throughput. It also has economic disadvantages due to its high cost.